DRAMs use internal bus lines with a large number of bits in order to obtain a high bandwidth. FIG. 1 illustrates a DRAM operating in ×16, ×8, ×4, ×2 and ×1 data input/output modes. If a DRAM having a bandwidth of 1.2 Gbps/s uses a 8-bit bus line per DQ pad, a DRAM having 16 DQ pads uses 16×8=128 internal bus lines.
In the ×16 mode, 8 data lines are coupled between a memory cell array block and 16 IO blocks and each IO block is coupled to 16 DQ pads. For example, memory cell data items transmitted to an IO block 14 through the 8 data lines are output to a DQ 14 pad. In addition, memory cell data items transmitted to an IO block 6 are output to a DQ6 pad, memory cell data items transmitted to an IO block 10 are output to a DQ10 pad, and memory cell data items transmitted to an IO block 2 are output to a DQ2 pad.
In the ×8 mode, 8 internal bus lines are arranged such that the 8 data lines that were coupled to the IO block 14 in the ×16 mode are connected to the IO block 6. In addition, 8 internal bus lines are arranged such that the 8 data lines that were coupled to the IO block 10 are connected to the IO block 2.
In the ×4 mode, 8, 16 and 32 internal bus lines are arranged such that the 8 data lines that were coupled to each of the IO blocks 14, 6, 10 and 2 in the ×16 mode are connected to the IO block 2. In the ×2 mode, 8, 16, 32, 40, 48, 56, 64 internal bus lines are arranged such that the 8 data lines that were coupled to each of IO blocks 14, 6, 10, 2, 12, 4, 8 and 0 in the ×16 mode are connected to the IO block 0. In the ×1 mode, maximum 128 internal bus lines are arranged such that the 8 data lines that were coupled to each of IO blocks 14, 6, 10, 2, 12, 4, 8, 0, 1, 9, 5, 13, 3, 11, 7 and 15 in the ×16 mode are connected to the IO block 0.
To support these various data input/output modes, a large number of data lines may be routed in a memory device. A plurality of data lines may be used if the data lines are operated in a voltage-driven mode. The plurality of data lines may represent overhead that occupies a considerably large part of the chip area of the memory device.